1. Field of the Invention
The present invention relates to a semiconductor charge pump circuit for generating a voltage which is higher than a supply voltage or a negative voltage, and a nonvolatile semiconductor memory device including such a semiconductor charge pump circuit.
2. Description of the Related Art
Conventionally, semiconductor memories, for example, EEPROMs (Electrically Erasable and Programmable Read Only Memories) and flash memories, require a voltage which is higher than a supply voltage or a negative voltage for read/write/erase operations. One of the following two methods are used to generate such a voltage: (i) applying an external voltage; and (ii) pumping a supply voltage by a charge pump circuit provided in a chip. Recently, the method of pumping a supply voltage by a charge pump circuit provided in a chip has become the method of choice since chips mostly include only one power supply today.
A basic principle of operation of a charge pump circuit will be described. FIG. 9 shows a change in the voltage of a capacitor C1 used for pumping. In an initial state, a first end of the capacitor C1 is supplied with 0 V, and a second end of the capacitor C1 is supplied with a supply voltage Vcc.
When the potential of the first end is changed from 0 V to the supply voltage Vcc, the supply voltage Vcc of the second end is doubled to 2xc3x97Vcc. Namely, the voltage of the second end is pumped to 2xc3x97Vcc. This is represented by expression (1).
Q1=Cxc3x97Vcc
Q2=Cxc3x97(2Vccxe2x88x92Vcc)=CVccxe2x80x83xe2x80x83(1)
In expression (1), letter C represents the capacitance of the capacitor C1. Expression (1) represents Q1=Q2; i.e., xe2x80x9cconservation of chargexe2x80x9d. The above-described basic principle of operation of a charge pump circuit can be applied to an LSI circuit. One generally known charge pump circuit for an LSI is a Dickson-type charge pump circuit.
FIG. 10 shows a representative configuration of a conventional Dickson-type charge pump circuit. In the example shown in FIG. 10, the conventional Dickson-type charge pump circuit includes five n-type MOS (metal-oxide-semiconductor) transistors D0 through D4 and four capacitors C1 through C4.
A basic pump cell of the Dickson-type charge pump circuit shown in FIG. 10 includes, for example, one capacitor C1 and one n-type MOS transistor D1, which are surrounded by a dashed line in FIG. 10. Four such basic pump cells, each including one capacitor (C1, C2, C3, C4) and one n-type MOS transistor (D1, D2, D3, D4), are connected in series so as to form the charge pump circuit.
The first-stage transistor D0 has a drain D and a gate G which are both connected to an output end of a power supply (supply voltage Vcc: for example, 3V). The transistor D0 acts as a backflow preventing valve for preventing an electric current from backflowing from a node N1 toward the power supply Vcc. The node N1 is connected to a source of the transistor D0 and has a pumped-up voltage.
The charge pump circuit receives clock signals CLK1 and CLK2 as input signals. The clock signal CLK1 is input to the capacitors C1 and C3, and the clock signal CLK2 is input to the capacitors C2 and C4. FIG. 11 is a timing diagram illustrating waveforms of the clock signals CLK1 and CLK2.
As shown in FIG. 11, the clock signals CLK1 and CLK2 each have an amplitude which is equal to the supply voltage Vcc. The clock signals CLK1 and CLK2 have opposite phases to each other. For example, when the clock signal CLK1 is at the supply voltage Vcc, the clock signal CLK2 is at 0 V. When the clock signal CLK1 is at 0 V, the clock signal CLK2 is at the supply voltage Vcc.
Returning to FIG. 10, a voltage pumped by the charge pump circuit is output from an output node Nout. Although not shown in FIG. 10, the output node Nout is connected to, for example, a regulator or a smoothing capacitor. A voltage which is pumped by the charge pump circuit (a positive high voltage in this example) is output to, for example, the regulator through the output node Nout.
FIG. 12 is a schematic cross-sectional view of an n-MOS transistor.
As shown in FIG. 12, a flash memory generally uses a p-type substrate. The n-type MOS transistor is formed as follows. The p-type substrate is provided with a reference voltage Vss (0 V). A source region S (n+) and a drain region D (n+) are formed in the p-type substrate with a prescribed distance therebetween. A gate G is formed on an area of the p-type substrate which is interposed between the source region S and the drain region D. The p-type substrate and the gate region G have an insulating layer therebetween. A plurality of n-type MOS transistors having such a structure are connected in series so as to form a charge pump circuit as shown in FIG. 10.
FIG. 13 is a timing diagram illustrating ideal waveforms of nodes N1 through N4 of a Dickson-type charge pump. As shown in FIG. 10, the node N1 is provided between the n-type MOS transistor D0 and the N-type MOS transistor D1, the node N2 is provided between the N-type MOS transistor D1 and the N-type MOS transistor D2, the node N3 is provided between the n-type MOS transistor D2 and the N-type MOS transistor D3, and the node N4 is provided between the N-type MOS transistor D3 and the N-type MOS transistor D4.
In an initial state where the capacitors C1 through C4 do not have any charge accumulated therein and the clock signals CLK1 and CLK2 are 0 V, voltages VN1 through VN4 of the nodes N1 through N4 are represented by expression (2).
VN1=Vccxe2x88x92Vth
VN2=Vccxe2x88x922Vth
VN3=Vccxe2x88x923Vth
VN4=Vccxe2x88x924Vthxe2x80x83xe2x80x83(2)
As can be appreciated from expression (2), each time the charge is transferred by an N-type MOS transistor so as to pump up the voltage of anode, the pumped-up voltage of the node is reduced by the threshold voltage Vth of an N-type MOS transistor (for example, about 0.6 V).
As shown in FIG. 13, when the voltage of the clock signal CLK1 is changed from 0 V to Vcc, the voltage of the node N1 is changed to 2Vccxe2x88x92Vth, and an output voltage of (2Vccxe2x88x92Vth)xe2x88x92Vthxe2x88x92Vb is transferred by the N-type MOS transistor D1 from the source of the N-type MOS transistor D1 to the node N2. xe2x80x9cVbxe2x80x9d represents a voltage drop of the transferred potential, the voltage drop caused by a substrate biasing effect. The voltage drop Vb increases in proportion to the sourcexe2x80x94substrate voltage VBS.
When the voltage of the clock signal CLK2 is changed from 0 V to supply voltage Vcc, the voltage of the node N2 is changed from 2Vccxe2x88x922Vthxe2x88x92Vb to 3Vccxe2x88x922Vthxe2x88x92Vb.
The above-described operation is repeated up to the node N4 as shown in FIG. 13, and the resultant voltage is output as an output voltage Vout from the charge pump circuit.
The output voltage of such a Dickson-type charge pump circuit (corresponding to the voltage of a node Nout) is represented by expression (3) as described in, for example, xe2x80x9cKi-Hwan Choi et al., 1997 Symposium on VLSI Circuits Digest of Technical Papers, 1997xe2x80x9d.                               Vout          ⁢                      xe2x80x83                    ⁢                      (            conventional            )                          =                                            Vcc              -                              Vth                ⁡                                  (                  0                  )                                                                    ⎵                              (                a                )                                              +                                                    ∑                                  i                  =                  1                                n                            ⁢                              {                                                                            (                      a                      )                                        ⁢                    Vcc                                    -                                      Vth                    ⁡                                          (                      i                      )                                                                      }                                                    ⎵                              (                b                )                                                                        (        3        )            
In expression (3), Vth(0) represents a threshold voltage of the N-type MOS transistor D0 (for example, Vth=0.6 V), and Vth(i) represents a threshold voltage of the nxe2x80x2th N-type MOS transistor. Term (a) of expression (3), i.e., xe2x80x9cVccxe2x88x92Vth(0)xe2x80x9d is practically xe2x80x9c1xe2x80x9d. xe2x80x9cixe2x80x9d is a natural number.
Vth(i) represents a threshold obtained in consideration of the substrate biasing effect. The larger the difference between the voltage of the source and the voltage of the substrate (in this example, the voltage of the p-well) is, the larger the value of Vth(i) is. In expression (3), Vth and Vb are independently represented (Vth+Vb≈Vth). In a structure including multiple-stage pumps, the term (a) of expression (3) is ignored and the effect of the term (b) is important. Based on the term (b), the voltage which is pumped for each stage of pump is represented by expression (4).
Vccxe2x88x92Vth(i)xe2x80x83xe2x80x83(4)
The output voltage Vout of the charge pump circuit is influenced by the margin of the threshold voltage Vth(i) of each transistor and the supply voltage Vcc. Accordingly, when the threshold voltage Vth(i) obtained in consideration of the substrate biasing effect is raised, the voltage which is pumped for each stage of pump is decreased or becomes zero. Therefore, even when the number of the stages of pumps is increased, the output voltage Vout becomes less likely to be increased or is not increased.
For example, in the Dickson-type charge pump circuit shown in FIG. 10, the voltage of the source of the N-type MOS transistor D4 is the output voltage Vout, and the potential of the p-well is Vss (0 V). Therefore, the threshold voltage of the N-type MOS transistor D4 is raised by the substrate biasing effect. Thus, the transfer efficiency, i.e., the pumping efficiency is decreased.
As can be appreciated from the above, a Dickson-type charge pump circuit, which is a general charge pump circuit, has the following two main drawbacks: (1) the threshold voltage is raised due to a substrate biasing effect; and (2) the amplitude of a clock signal for determining the level of pumping is converged to the supply voltage Vcc; i.e., when the supply voltage Vcc is low, the pumping efficiency is decreased.
In order to prevent the above-described drawbacks of the conventional Dickson-type charge pump circuit, the following two are indispensable: (1) restriction of arise in the threshold voltage of the MOS transistors, which is caused by the substrate biasing effect; and (2) an increase in the margin between the supply voltage Vcc and the threshold voltage Vth(i) of the nxe2x80x2th MOS transistor.
In the conventional Dickson-type charge pump circuit, as shown in FIG. 10, the substrate potentials (p-well potentials) of all the N-type MOS transistors D1 through D4 are Vss (0 V), and the amplitudes of the clock signals CLK1 and CLK2 are both equal to the supply voltage Vcc. Therefore, the transfer efficiency of the pumping voltage is deteriorated due to the substrate biasing effect In addition, the first-stage basic pump cell performs pumping only to corresponding to the supply voltage Vcc, which is equal to the amplitude of each clock signal. This also deteriorates the pumping efficiency.
According to one aspect of the invention, a semiconductor charge pump circuit includes basic pump cells connected in N stages where N is a natural number of equal to or greater than three. Each cell is formed by connecting a control terminal of a transistor and a first driving terminal of the transistor and connecting the control terminal and a first end of a capacitor. The basic pump cells are connected in N stages by connecting a second driving terminal of a transistor of one basic pump cell to a first driving terminal of a transistor of a next-stage basic pump cell. A second end of the capacitor of each basic pump cell receives a clock having a different phase from a clock which is input to the capacitor of an immediately previous-stage basic pump cell and the capacitor of an immediately subsequent-stage basic pump cell. The basic pump cells connected in N stages are driven at a plurality of phase timings so as to pump a voltage. The transistor of at least one of the basic pump cells includes a substrate well. The semiconductor charge pump circuit further includes a switching element for applying, as a clock, a voltage waveform of the basic pump cell, immediately previous to the inverter, to a second end of a capacitor connected to a control end of the transistor including the substrate well and to the substrate well of the transistor during a pumping operation, the voltage waveform being pumped with the same phase timing of that of the voltage of the capacitor on the side of the control terminal of the transistor connected to the capacitor.
In one embodiment of the invention, the basic pump cells connected in N stages include a group of basic pump cells operating with the same timing as each other. An externally input basic clock for transfer is applied, as a voltage waveform, to a substrate well of a transistor, and to a second end of a capacitor, of a first-stage basic pump cell of the group of basic pump cells.
In one embodiment of the invention, two-phase clocks having opposite phases to each other are used.
In one embodiment of the invention, the switching element is an inverter circuit including a P-type MOS transistor and an N-type MOS transistor, and switches between the voltage waveform of the basic pump cell immediately previous to the inverter circuit and a reference voltage, in accordance with the level of the clock.
In one embodiment of the invention, a difference between (i) a voltage applied to at least one of the substrate well of the transistor or the second end of the capacitor connected to the transistor during the pumping operation, and (ii) the voltage pumped with the same phase timing as the voltage is restricted up to a threshold voltage of the P-type MOS transistor.
In one embodiment of the invention, the basic pump cells connected in N stages include at least one basic pump cell, having an N-type MOS transistor formed in and on a p-substrate, and at least one basic pump cell, having an N-type MOS transistor formed in and on a p-well which is electrically separated from the p-substrate.
In one embodiment of the invention, the semiconductor charge pump circuit has a triple-well structure in which the p-well is surrounded by an n-well so as to be separated from the p-substrate, the semiconductor charge pump circuit further comprising at least one transistor in and on the p-substrate.
According to another aspect of the invention, a nonvolatile semiconductor memory device includes any one of the above-described semiconductor charge pump circuits.
According to the present invention, a switching element such as, for example, an inverter circuit is added to the conventional Dickson-type charge pump circuit so as to increase the amplitude of a clock signal, and the clock signal is input to a substrate well of an N-type MOS transistor. Thus, the pumping capability and the pumping efficiency are improved. A charge pump circuit according to the present invention has an improved transfer efficiency of the pumping voltage as compared to the conventional Dickson-type charge pump circuit, and realizes efficient pumping even with a low voltage power supply.
Thus, the invention described herein makes possible the advantages of providing a semiconductor charge pump circuit for improving the transfer efficiency of the pumping voltage over the conventional Dickson-type charge pump circuit so as to be capable of pumping even with a low voltage power supply, and a nonvolatile second memory device including such a semiconductor charge pump circuit.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.